This invention relates to apparatus for receiving digital data communications, and more particularly to circuitry which produces from an asynchronous data input a detected output synchronized to a local clock.
In digital data communications systems, the incoming signal is normally amplified and the information-containing data pulses are then detected by setting the state of a digital logic circuit, such as a latch, often in synchronization with a first local clock. In many systems, the detected reception is used to drive succeeding circuitry which is synchronized to a second clock, and the detected state of the incoming data must be established before the next clock pulse of the second clock in order for the succeeding circuitry to function properly. It is therefore necessary that the detection of the asynchronous data and its time synchronization to the first clock take place rapidly enough so that the state of the input is established without ambiguity before a pulse of the second clock.
A common mechanism used to provide both synchronization and detection involves driving a digital latch with a pair of inputs (SET and CLEAR), each derived independently from both the amplified input and the first clock. One implementation of the drivng circuitry generates a SET input when the asynchronous input pulse and the clock pulse exist simultaneously and generates a CLEAR input whenever the clock pulse is present and the asynchronous input pulse is absent. This arrangement is, however, often unsatisfactory since two inversion-gate delays are inherent in the independent generation of the SET and CLEAR inputs, and this two-gate delay may cause the detection (setting or clearing of the latch) to be completed significantly after the end of the pulse of the first clock to which it is synchronized.
This problem is most severe, of course, in multiple clock systems when the asynchronous input changes state in the middle or near the end of a synchronizing clock pulse. In these cases, the latch could start to switch as late as the trailing edge of a first clock pulse and the remainder of the switching delay would have to take place during the separation between the pulse of the first clock and the succeeding pulse of the second clock, if the system is to operate properly. Large time separation between the two clocks have been suggested, but for many systems with high operating frequencies, the maximum separation between clock pulses is not very large compared to the total gatedelay inherent in the driving circuitry. Conversely, reduction in gate delays necessitates large amounts of power consumption as well as large chip area if the circuit is fabricated as an integrated circuit using Metal Oxide Semiconductor transistors, hereafter referred to as a MOS circuit.
Accordingly, driving the latch with independently generated SET and CLEAR inputs does not provide the detection and synchronization adequate for many data communications systems. In particular, such a technique is difficult to implement in integrated circuitry suitable for operation at high frequencies.
It is therefore an object of the present invention to provide an improved detector-synchronization technique capable of receiving an asynchronous input and producing a detected output synchronized to a local clock without the abovementioned disadvantages.
It is a particular object to provide an integrated circuit for rapidly performing detection of an asynchronous input and synchronization of it to a local clock so that in two clock systems the need for large time separation between the clocks is reduced.
It is an additional object of the invention to provide the synchronization and detection using a MOS integrated circuit which is operable at high frequencies and does not dissipate excessive amounts of power.
It is a further object of the invention to provide such a circuit with capabilities of unambiguously detecting a change of state in an incoming digital pulse train during the clock pulse to which it is synchronized or shortly thereafter.